1. Field of the Invention
This invention relates generally to semiconductor devices, and more particularly, to a method of fabricating a semiconductor device having a self spaced contact.
2. Description of Related Art
Higher circuit density and faster switching speed have been a major focus of recent developments in semiconductor technology. There are two related factors that limit the switching speed of semiconductor devices. First, the parasitic resistance between, for example on a bipolar transistor, the base contact and the active area of the transistor. Secondly, the parasitic capacitance between the base region and the collector region, for example. Each time the transistor switches, the base current charges or discharges the parasitic capacitance. The base current is further impeded by the parasitic base resistance. The speed of the semiconductor device is increased by reducing the product of the parasitic base resistance and the parasitic capacitance.
Metal Oxide Semiconductor (MOS) devices are also susceptible to parasitic capacitances and parasitic resistances. Further, as these devices are often used for memory devices, they typically have a great number of repetitive cells and are substantially large.
A number of different prior art processes have been disclosed for fabricating improved semiconductor devices. U.S. Pat. No. 5,098,854, to Kapoor et al., discloses a process for forming a self-aligned silicide base contact structure for bipolar transistors. The disclosed structure includes a base region, a polycrystalline silicon emitter contact region, a spacer oxide, and a base contact formed of metal silicide. The spacer oxide electrically isolates the side walls of the emitter contact region from the upper surface of the base region. The metal silicide is formed by first depositing a metal layer on the upper surface of the base region, then heat treating. Heat treating causes the metal atoms to diffuse into the underlying silicon substrate, and the silicon atoms diffuse into the overlying metal layer, thus forming an electrically conductive compound.
U.S. Pat. No. 5,106,783, to Chin et al., discloses a process for fabricating a semiconductor device having self-aligned contacts. The disclosed process provides a digitated electrode having a contiguous conductive region that contacts underlying first and second semiconductor regions. The second semiconductor region underlies a finger of the electrode. The contiguous conductive region enables the first semiconductor region to contact the second semiconductor region with a common electrode, and further self-aligns the common electrode with the digitated electrode.
U.S. Pat. No. 4,745,080, to Scovell et al., discloses a method of making a self-aligned bipolar transistor. The disclosed device is achieved by providing oxidized sidewalls of an emitter mesa as part of a p+ base contact implantation mask. Collector contact alignment is achieved by using oxidized sidewalls of polycrystalline silicon alignment mesas defined in the same polysilicon as the emitter mesa, but deposited on oxide, rather than the implanted base region.
Known patents for fabricating semiconductor devices that might be considered to have a degree of relevance to the present invention are U.S. Pat. Nos. 5,175,127; 5,100, 838; 5,149,664; 5,049,525; 4,883,767; 4,966,858; 5,217,913; 4,992,387; and 5,028,555.
Although the semiconductor devices disclosed in the above enumerated prior art references have improved switching speed and dimensional scaling, they fail to disclosed all of the advantageous features achieved by the present invention.